Electronic signals within large integrated circuits suffer from substantial propagation delays upon being transmitted across the circuit areas. The propagation delays are a function of distance and are due to the parasitic reactances, the small but finite wire resistances and transistor switching times. The problem is further complicated by the fact that these delays are distributed across the area of the integrated circuit such that their effect on the propagation of the signals is typically not evenly felt everywhere within the area of the circuit. This effect is most readily seen in the timing of digital circuits that operate using a periodic square-wave clock signal to control the timing of the operations of a digital integrated circuit. After having originated in one part of an integrated circuit, a clock signal will be noticeably out of phase with its source by the time it reaches a point within the integrated circuit substantially far away from its source. This problem is commonly referred to as clock skew and leads to errors in the propagation of signals across the circuit. Various approaches to skew compensation across a single large clock domain can be used, but these approaches typically suffer from inefficiencies in that once a sufficient clock skew has occurred data often must wait for subsequent clock cycles in order to propagate in phase with the clock. Conversely, some approaches involve the reduction of the clock frequency so that purely on a time scale basis the clock and propagation delays become small in comparison to the clock period to mitigate the effects of clock skew. Using those approaches a clock rate which minimizes the effects of clock skew is limited by the propagation delay. Lowering the clock rate is, however, undesirable because it reduces the processing speed of the integrated circuit.
An approach using H-trees has been used in an attempt to solve problems associated with clock skew and phase delay. This particular approach is a way of dividing up a circuit area and having paths, which are of equal length to all points in the circuit. For example, the path distance from the center of a first H of an H-tree to the tip of an edge of the H is the same for all four tips of the H. If each of the tips of each edge of the first H is located at the center of a respective smaller H, the path length from the center of the first H to the sixteen tips of the smaller H's is the same. If one covers the area of a circuit in this recursive manner, the final tip points of the numerous smallest H's of the H-tree will all be the same distance from the center of the first H of the H-tree. This can be used to ensure that the clock arrives at all points substantially simultaneously. Half of the problem however remains unsolved. Although the problem of clock synchronization is solved, the data set will end up out of synchronization with the clock. In the context of large area circuits, however, this approach does not solve the problems. In such a case, even if one sends data synchronous with the clock, by the time it arrives at a remote position it is out of sync with the clock at that position.
One more effective approach to compensate for clock skew, or more generally propagation delays, is to divide an integrated circuit occupying a large area into a number of smaller discrete functional modules or cells. Each cell is made small enough so that propagation delays are small enough such that a single timing domain or clock domain can control transmission through that cell. In this approach, there exist multiple clocks within the same integrated circuit, one for each cell the integrated circuit is divided into. Each cell can then be considered as having its own clock domain.
Sub-dividing the integrated circuit into cells each having its own clock domain to facilitate high-speed data transfer amongst the cells adjacent to one another can be done with clocks of adjacent cells being synchronized to one another, but this requires integral numbers of clock cycles between cells creating unnecessary delays for short inter-cell connections or for signals that cross many cells. Hence the rate of data propagation can be limited by the clock frequency. Another technique is for the cells not to be synced and to have inter-cell signals cross these unsynchronized clock domain boundaries, but this requires substantial amounts of synchronization circuitry to align signals to the clocks of different cells. All of this additional circuitry for synchronization limits the amount of area on the substrate that can be used for the intended purposes of the integrated circuit.
It would be desirable for there to be an arrangement and management of timing various domains on an integrated circuit which minimizes the problems of clock skew and the associated effects of slowing data propagation, and reducing clock frequencies current solutions introduce.